Field of the Invention
Embodiments of the present invention generally relate to chip packaging, and in particular, to a through-silicon-via (TSV) interposer and integrated circuit (IC) die.
Description of the Related Art
Conventional chip packaging schemes often utilize a through-silicon-via (TSV) interposer to enable a plurality of integrated circuit (IC) dies to be mounted to a single organic substrate. The interposer generally includes an interconnect wiring layer disposed on a core. The interconnect wiring layer is coupled by micro-bump solder connections to the various dies disposed on the interposer. Since the interposer is generally very thin, it is susceptible to damage, and particularly cracking during handling after soldering steps of the fabrication cycle.
One conventional process for increasing the stiffness of the interposer to reduce damage is to laminate one or more stiffening layers to the interposer. However, the laminated stiffening layers increase material costs and complicate the fabrication sequence, thus undesirably increasing the manufacturing cost of the interposer. Another conventional process for increasing the stiffness of the interposer is to bond a prefabricated stiffening ring on the surface of the interposer. However, adding a prefabricated stiffening ring will also increase material costs and complicate the fabrication sequence, which as discussed above, undesirably increases the manufacturing cost of the interposer.
Therefore, a need exists for an improved interposer and methods for fabricating a chip package utilizing the same.